The present invention relates to a hafnium alloy target having favorable deposition property and deposition speed, which generates few particles, and which is suitable for forming a high dielectric gate insulation film such as a HfO or HfON film, as well as to the manufacturing method thereof. Incidentally, the unit of “ppm” as used in this description shall mean wtppm in all cases.
The film thickness of a dielectric gate insulation film is largely influenced by the performance of a MOS transistor, and it is essential that the interface with the silicon substrate is electrically smooth and that the mobility of the carrier does not deteriorate.
Conventionally, a SiO2 film has been used as this gate insulation film, and was the most superior in terms of interfacial quality heretofore. In addition, there is a characteristic in that the thinner the SiO2 film used as this gate insulation film, the number of carriers (that is, electrons or electron holes) increases, and the drain current also increases thereby.
From the foregoing circumstances, each time the power supply voltage would decrease as a result of miniaturizing the wiring, the gate SiO2 film has been consistently formed as thin as possible within a range that would not deteriorate the reliability of dielectric breakdown. Nevertheless, a tunnel leakage current flows directly when the gate SiO2 film is formed of a thickness of 3 nm or less, and a problem arises in that this film would not function as an insulation film.
Meanwhile, although attempts are being made to miniaturize the transistor, so as long as there are limitations in the film thickness of the SiO2 film, which is the gate insulation film as described above, miniaturization of the transistor loses its significance, and a problem arises in that the performance is not improved.
Moreover, in order to lower the power supply voltage of the LSI as well as lower the power consumption, it is necessary to make the gate insulation film even thinner. Nevertheless, since there is a problem regarding the gate dielectric breakdown when the film thickness of the SiO2 film is made 3 nm or less as described above, thinning of the film had a limitation in itself.
In light of the above, as a candidate for the next-generation gate insulation film, HfO and HfON having a higher dielectric constant in comparison to a conventional SiO or SiON are being considered as a strong candidate. This film is deposited by subjecting a Hf target to reactive sputtering with oxygen or nitrogen.
Several patent applications; for instance, a patent application pertaining to the target to be used in such deposition, manufacturing method thereof and formation of an oxide film (c.f. Japanese Patent Laid-Open Publication No. H11-40517), and patents relating to a semiconductor element (c.f. U.S. Pat. No. 4,333,808, U.S. Pat. No. 6,207,589) have been disclosed.
Patent document Japanese Patent Laid-Open Publication No. H4-358030 describes that the impurities of a Hf target are Al: 10 ppm or less. Further, patent document Japanese Patent Laid-Open Publication No. H8-53756 and patent document Japanese Patent Laid-Open Publication No. H8-60350 describe that the impurities are Fe: 10 ppm or less, Ni: 10 ppm or less, Cr: 10 ppm or less, and Al: 10 ppm or less.
Patent document EPO 0915117 describes that the impurities are Fe: 10 ppm or less, Ni: 10 ppm or less, Cr: 10 ppm or less, Al: 10 ppm or less, oxygen: 250 ppm or less, Na: 0.1 ppm or less, K: 0.1 ppm or less, U: 0.001 ppm or less, and Th: 0.001 ppm or less.
Further, it has been indicated that it is necessary to limit the impurities of Fe, Ni, Cr, Na, K, U and Th in a MoSi, WSi or Ti film used to form portions in the extreme vicinity of a gate electrode, drain or source, and there are descriptions of technology for prescribing the amount of impurities in the target (c.f. Japanese Patent Laid-Open Publication No. S60-66425, Japanese Patent Laid-Open Publication No. S61-107728, Japanese Patent Laid-Open Publication No. S61-145828, Japanese Patent Laid-Open Publication No. H2-213490, Japanese Patent Laid-Open Publication No. H4-218912).
Nevertheless, each of the foregoing conventional technology only prescribed certain impurities regarding the elementary substance Hf.
As a result of research concerning the deposition of an insulation film using a Hf target, there was a problem in that numerous particles were generated during deposition with a conventional single type elementary substance Hf. With this, it was difficult to reduce the number of particles to practical level even when the processing of suppressing the peeling of a film, which often occurs during the deposition of a metal film with strong adhesiveness known as pasting was performed, upon depositing TiN with a Ti target.
Further, in particular, when the amount of Fe, Ni or Cr is several ppm, it has been discovered that these elements diffuse to the Si substrate portion under the gate electrode, and deteriorate the device property. Moreover, there is variation in the thickness of the deposited insulation film, and there is a problem in that the device property of the wafer and other components would become varied.
A process referred to as burn-in is performed at the initial stages of sputtering, and the film thickness would not be stable unless the integral power consumption is 20 kWHr or more.
Further, in order to improve the deposition property and deposition speed in the future, although the increase in sputtering power may be considered, in such a case, with a conventional bonding method that uses brazing filler metal, it is anticipated that the brazing filler material will dissolve and the target would peel thereby.